1. Technical Field
Some embodiments disclosed herein are related to a method and apparatus for data compression and, in particular, to compression of the configuration bitstream of field programmable logic.
2. Discussion of Related Art
Field programmable logic (FPG) is capable of being programmed by the user (in the “field”) using a configuration bitstream generated by a software tool. When the IC containing field programmable logic is used in a system, it utilizes a non-volatile memory to store the configuration bitstream. This non-volatile memory may be a separate memory chip, or it may be incorporated into the FPG chip. In either case, the size of the memory utilized in the system is related to the size of the expected bitstream and impacts the bill of materials (BOM) of the system.
In the case of on-chip non-volatile memory, there may be limits to the size of the memory that can be economically used. Therefore, the size of the configuration bitstream could determine the overall feasibilty of the product. The size of the configuration bitstream also impacts the speed at which the FPG can be programmed.
The speed of programming and memory sizes are also important in the context of silicon testing of the FPG IC because programmable logic, by nature, utilizes tens of bitstreams for sufficient testing coverage. The cost of a silicon test on an Automatic Test Equipment (ATE), or similar equipment, is highly sensitive to the test time and memory requirements, both of which are primarily set by the size of the configuration bitstream. A field programmable logic IC with a smaller bitstream will have a cost advantage over other systems.
Therefore, there is a need for a method of compressing and decoding data for utilization, for example, in an FPGA that reduces the size of the input data and decreases the overall write time.